A conventional display apparatus needs to convert image data, e.g., input frames, received from a video signal source to output frames that may have a different resolution compared to the input frames, consistent with display timing determined by an internal display controller so as to display the output frames on a panel or screen. In order to achieve frame synchronization where output frame rate is synchronized with input frame rate, the conventional display apparatus adjusts an output vertical synchronous (output v-sync) signal needed for displaying the output frame according to an input vertical synchronous (input v-sync) signal provided by the video signal source. When a pulse of the input v-sync rises, a pulse of the output v-sync is synchronously generated which means the output v-sync is reset to force the output v-sync to be synchronized with the input v-sync. However, such an approach to display timing control may cause problems. For example, the output v-sync signal is forced to change in order to start the next cycle even though the present output cycle is not complete. As a result, the last few scan lines of the present output frame are not updated before the new cycle starts. For some low timing tolerance display devices, incomplete scan lines of frames can cause undesirable display effects.